Working with Xilinx's DD3 Core:
Click here to access Xilinx DDR3 Core tips and hints

First Inversion specializes in high performance, complex, or otherwise demanding FPGA and CPLD designs.
First Inversion is your solution for the most difficult FPGA designs.

Fitting a design into the smallest and cheapest part in clever ways is no longer the most challenging aspect of FPGA designs. More often, designing entire systems, quickly, into one or a few large parts is the dominant challenge. Aspects of system-on-chip (SOC) design include the ability to quickly integrate 3rd party IP cores using standard protocols, design complex signal processing systems, high performance state machines and arbiters, and communicating using on-chip switch fabric.

Does this sound good? Does this sound difficult? Look what we’ve done recently. Take a look at our white papers, design examples, and the skills listed below.

  • DSP in an FPGA, including the design of DDS, filter, DUC, DDC, De-Spreading, and Correlation
  • Bus interface and bridge design
  • Video and Audio Processing
  • Memory and Bus Arbitration
  • Digital Architecting and Optimized Logic Partitioning
  • Datacom Framing and De-Framing, Clock & Data Recovery, Test and Impairment Generation
  • Data Acquisition and Processing
  • DDR3/DDR2 Interfacing and IP Core Implementation

We are proficient in VHDL, Verilog, all major synthesis and simulation tools, MATLAB, System Generator and DSPBuilder, and the tools and device technology of all the major FPGA and CPLD vendors.


     Fractional Sample Rate Converter
       click for details

       click for details

     Time Domain Correlator
       click for details

home | about | contact | tools | technologies | tutorials | white papers| Sitemap